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Yaboze
08-12-08, 10:44 AM
Ok, let's say a E8400 has 6 meg cache and a Q9450 as 12 meg. With the E8400, does it share the cache between the 2 cores? Is it even 3 meg for each? Or can 1 core use all of it? Same question on the Q9450.

Just trying to understand if the processor uses all available or it divides it evenly.

walterman
08-12-08, 12:26 PM
On the core 2 duo processors, the L2 cache is shared between the 2 cores in the die.

Intel optimized the cache to allow simultaneous operations of both cores. Both cores can operate in the same area of memory, with just one copy of the data in the cache. This increases the cache efficiency. The cache also is also dinamically allocated by each core, so, if one core is idling, the other core can use more cache for itself.

On the core 2 quad processors, there is no L3 cache. Basically you have 2 'core 2 duo' dies into 1 chip, interconnected by the FSB. Here you need to use classic cache coherency techniques like snooping (basically, each cache monitors the address lines, of the rest of caches, for accesses to memory locations that they have cached). This protocol increases the traffic in the FSB, cause the caches need to exchange tags & data between them.

Hope this helps :)