Ati's next gen VPU (loci).

[Gar]

Here is a little tid bit from rage, I'll post as it seems very interesting for a .13 part.

Link (http://www.nasdaq.com//asp/quotes_news.asp?logopath=http%3a%2f%2fcontent.nasd aq.com%2flogos%2fATYT.GIF&pageName=Company%20News&selected=ATYT&consumer=NDQ&StoryTargetFrame=_top&market=Nasdaq-NM&coname=ATI%20Technologies%20Inc.&symbol=NVDA`&symbol=INTC`&symbol=CREAF`&symbol=ATYT`&symbol=OVER`&symbol=ATVI`&symbol=AMD`&symbol=HAS`&cpath=20030514\200305140902CTXBIZ37086236.htm)

ATI's visual processing unit (VPU) has more than 200 million transistors of digital logic. A design of this size and complexity requires not only extremely high stuck-at fault coverage, but also thorough testing for delay-related defects, the preponderant defect type in 0.13 micron process geometries and below. Using basic scan methods, excellent delay test requires up to 6X more tester time than required for stuck-at faults, which already is at an unacceptable cost of test.

200 million transistors is quite a few for a .13 micron part. I wonder how different it is gonna be from ATI's current R3x0 chips. It uses its current tech, but will be drastically different (if that makes any sense). Either way, its expected for a fall release. Guess well see if they can pull it out in time.

[Ninja Prime]

Nice find. Sounds like it's gonna be a 8 vertex engine, 8x2 or 16x1 design... Probably won't be clocked real high, I bet it'll be at or under 500MHZ.

[PreservedSwine]

Loci is to be based on R350 tech. The big change (architecturally ) is supposed to come w/ the R500

[Uttar]

Considering 200M+ transistors, that GOTTA be a 16x1 and 8 VS architecture... Woah...
Well, I guess this is refering to the R500 anyway, so saying 16x1 is wrong, since it got dynamic resource allocation.


Uttar

[Ninja Prime]

since it got dynamic resource allocation.

That's short for "Totally Sweetness!"

[Lezmaka]

Originally posted by Gar
200 million transistors is quite a few for a .13 micron part.


The thing is, it never actually says it's a .13u part.

the preponderant defect type in 0.13 micron process geometries and below

The means it could be .13u or lower, but never says what the process actually is.

[marcocom]

LOL why not just make it 'a Be-jillion transistors'!

i hope ATi gets some kind of SMP support for dual/hyperthreaded cpu . maybe i could buy one next year to replace my 5800U as a workstation/gaming solution. 8x2/16x1 gets my dick hard (but not that monkey).

oh yea, and if they can just move their headquarters and bond holdings to the U.S. too - thanks. perfect. then i will try one and feel better about it.

oh and they gotta break the 1ghz barrier as well and we will have a happy feelings...cuz i dont want to downgrade my clockspeeds.

[jbirney]

What about the "texture computer" stuff (pritive processor that was suppose to be in the next gen stuff)??

[Hanners]

Originally posted by Uttar
Considering 200M+ transistors, that GOTTA be a 16x1 and 8 VS architecture... Woah...
Well, I guess this is refering to the R500 anyway, so saying 16x1 is wrong, since it got dynamic resource allocation.


Uttar

My guess is that the statement in question is about 'Loci'. From what I've heard it's more than likely going to be 8x2, not 16x1.


Originally posted by jbirney
What about the "texture computer" stuff (pritive processor that was suppose to be in the next gen stuff)??

That should be turning up in R500.

[Paul]

Seems fairly obvious to me that this isn't Loci.

[StealthHawk]

Originally posted by Paul
Seems fairly obvious to me that this isn't Loci.

This is R500.

[MrNasty]

This is zombocom !

[Paul]

Originally posted by StealthHawk
This is R500.

Hence i made the point that it was fairly obvious ;)

[MuFu]

Originally posted by Paul
Seems fairly obvious to me that this isn't Loci.

Why?

MuFu.

[M_W_M]

Originally posted by MuFu
Why?

MuFu.

Assuming the ratio of logic to cache was maintaned from the R300/350, wouldn't a 200 Million .13 micron part consume too much power and generate too much heat to be clocked competitively, plus have a very uneconomical die of more than 300 mm^2?

Surely this would have to be a .09 micron part, or do you know something different?

[Uttar]

Originally posted by MuFu
Why?

MuFu.

Now THAT'S what I call suggestion, hehe.
Well, if that's Loci, you can remain fairly confident ATI will have to delay it until Q1 2004 because I'd be very surprised if TSMC could manufacture that type of thing with more than 0.1% yields in 2003...


Uttar

[muzz]

Originally posted by marcocom
LOL why not just make it 'a Be-jillion transistors'!

i hope ATi gets some kind of SMP support for dual/hyperthreaded cpu . maybe i could buy one next year to replace my 5800U as a workstation/gaming solution. 8x2/16x1 gets my dick hard (but not that monkey).

oh yea, and if they can just move their headquarters and bond holdings to the U.S. too - thanks. perfect. then i will try one and feel better about it.

oh and they gotta break the 1ghz barrier as well and we will have a happy feelings...cuz i dont want to downgrade my clockspeeds.

Bahahaha!!! " Down Monkey- Bad Monkey"... heheheh

[bloodbob]

Originally posted by Uttar
Considering 200M+ transistors, that GOTTA be a 16x1 and 8 VS architecture... Woah...
Well, I guess this is refering to the R500 anyway, so saying 16x1 is wrong, since it got dynamic resource allocation.


Uttar

Meh I'll quote you for talking about number of piplines ( could have qouted other ppl )

Another alternate possiblity of the large transistor size is much large on chip memory.

[Ninja Prime]

Another alternate possiblity of the large transistor size is much large on chip memory

Although I find that very unlikely, it is possible. Using DRAM or maybe even 1T-SRAM, they could throw on 8MB of on-die memory, which would take up about 66 million transistors which would be packed very densely, making the chip do-able at .13 micron. That would leave around 140 million logic transistors, which would probably be about the right size for a beefed-up, 8x2, R350-based design.

[Uttar]

Originally posted by bloodbob
Meh I'll quote you for talking about number of piplines ( could have qouted other ppl )

Another alternate possiblity of the large transistor size is much large on chip memory.

Actually, don't. I might have had to be clearer: There GOTTA be some dynamic resource allocation there... ( read: no VS/PS traditional pipelines )
That is, I think, might be wrong.


Uttar

[Nebuchadnezzar]

Originally posted by Ninja Prime
Although I find that very unlikely, it is possible. Using DRAM or maybe even 1T-SRAM, they could throw on 8MB of on-die memory, which would take up about 66 million transistors which would be packed very densely, making the chip do-able at .13 micron. That would leave around 140 million logic transistors, which would probably be about the right size for a beefed-up, 8x2, R350-based design.

8 MB would take MUCH more than 66 million, in the 200-300M.

[Ninja Prime]

8 MB would take MUCH more than 66 million, in the 200-300M.

How so? Unless they used normal SRAM, then yeah probably.

[rwolf]

Perhaps loci is dual R350 cores in .13 microns. That would explain the 200+ million transistor count and the rumors of double the performance. We all know that the R350 was designed to support multiple cores.

Maybe ATI is using their cut/past design tool build loci.

Of course this is just speculation....

[Paul]

AFAIK, Loci is getting the extra speed from pipeline changes (previously 8x1, now 8x2 - 16x1 is very doubtful) and core/memory speed boosts, rather than adding a second chip. Yes the chipset supports that type of configuration, but then again so do other ATi and nVidia (i think) chipsets.

[PreservedSwine]

Originally posted by MuFu
Why?

MuFu.

:confused: