PDA

View Full Version : Inside the XBOX360 Part 1


Ruined
05-26-05, 09:29 PM
http://arstechnica.com/articles/paedia/cpu/xbox360-1.ars/1?54716

awesome read!!

Clay
05-26-05, 09:34 PM
This does look like a good article, thanks for the link!

Ruined
05-26-05, 09:52 PM
This does look like a good article, thanks for the link!

here are some excerpts that especially warrant discussion (though its worth digesting the whole article):

"In a move that surprised all of us, Microsoft tapped IBM to design the microprocessor that powers the Xbox 360. IBM drew on the results of the same Broadband Processor Architecture (BPA) initiative that produced the Playstation 3's Cell processor in order to furnish the next-generation Xbox with a truly next-generation core that looks set to last at least the five-year life of the average game console."

"Since at least 2003, Microsoft has been talking up the idea of "procedural synthesis" in games. In addition to the information on the technique provided in interviews, Microsoft has filed a very detailed patent that outlines how this will work on the Xbox 360. Since the unvieling of the new console and the confirmation of many details that had previously been only unconfirmed rumor, it's now possible to read this patent with the actual Xbox 360 implementation details in mind in order to learn exactly what Microsoft's ideas for procedural synthesis are and how those ideas function in their next-generation console.

In a nutshell, procedural synthesis is about making optimal use of system bandwidth and main memory by dynamically generating lower-level geometry data from statically stored higher-level scene data."

"If this idea of small pools of per-thread private, local storage that is accessible to the GPU via switching network sounds familiar, then you must have read my Cell coverage. This is essentially what the SPE local storage provides for the Cell's individual SPE. Xenon achieves this same effect using the L2, and Xenon's scheme has the advantage that it is more dynamically adaptable to the needs of the application, since it's a single store that can be partitioned dynamically. However, what the Xenon gains in adaptability it loses in flexibility, since unlike the SPE local storage, which is just a flat memory space that can be used in any way the programmer sees fit, the Xenon's write buffers can only be configured in one specific way and for one specific purpose (as described above).

Before finishing off the topic of locked sets in the L2 cache, it's important to note that while I may have gleaned this information from a Microsoft patent, a similar technique is already in use in an IBM chip: the Nintendo Gamecube's "Gekko" processor. The Gekko allows a programmer to lock half of the chip's 32KB, 8-way set associative L1 cache to prevent streaming writes from polluting the L1. Data from the locked half of the L1 bypasses the L2 entirely and goes directly to the Gekko's bus interface unit and out onto the memory bus.

The Gekko's L1 cache locking scheme doesn't provide the same degree of control and flexibility as the Xenon's L2 cache locking scheme described above, but it doesn't have to. Gekko is a single-issue, single-threaded design, whereas Xenon can have up to six simultaneous threads running."

"In all, the Xbox 360's procedural synthesis capabilities show great promise. Of course, the big question is going to be how many polygons per second can it produce in real-time. It's way too early to tell what percentage of the polygons in the average scene will be procedurally rendered, or what kind of impact this technique is going to have on the first generation of games. But perhaps we'll get some hard data once the first generation of games are out and developers can talk in more detail about the hardware and what it can do."