View Full Version : Can Nforce2 w/xp3200+ handle 2-2-2-5?
07-10-05, 08:01 PM
Hey folks, in the near future (next 2 months) I plan to upgrade to an Athlon64 which will call for a new mobo, memory and video card (pci-e x16). However, at the moment I'm thinking about purchasing the memory right now while the $15 rebate is available for the OCZ Gold Series 1GB (2 x 512MB) (http://www.newegg.com/Product/Product.asp?Item=N82E16820227211) at Newegg.
The specs indicate that it can be run at 2-2-2-5 timings @ 2.8v. What I'm wondering is if those timings can be reached with an old MSI Nforce2 Ultra 400 running a XP3200+ (400). I've checked the bios of my mobo and it allows manual settings of 2-2-2-5 but I'm under the impression that the CPU's memory controller will influence how agressive you can set the memory timings. Is this correct? Will the CPU hold me back? Has anyone run 2-2-2-5 timings on an old Athlon XP?
Any help would be appreciated. Thanks
The Athlon XP relies on the nForce2 chipset for managaing the memory. The A64 made the jump to integrated memory controller.
Depending on your cases coling and how well the Northbridge can handle the timings, you may be able to hit that low latency level. Regardless, the new memory will be ready to go for your new system.
07-10-05, 11:42 PM
Look at system2 in my sig. I think it's running at 2-2-2-7 though. Probably could do 2-2-2-5, but current timings seem to work best.
OCz should do the same.
07-11-05, 02:06 AM
you can most definitly run 2-2-2 i ran it on my dfi nf2 board as well as my asus nf3 board.
and just a little FYI: mushkin explains the TRAS value (last value listed) some people actually get better bandwidth from a higher value of around 10-12 with nf2 boards
I copied this from another board which was copied from mushkins site:
What is tRAS and why is it backwards and important at the same time?
The word latencies is generally used to describe a delay. However, Merriam-Webster defines the word’s origin as period of dormancy and in technical parlance, latency is often used to describe simply the duration of any event. One example is the PCI latency which describes the time any device has access to the PCI bus before it will be automatically disconnected to allow other devices access to the same resources.
Why are we talking about this? Very simple, the access latencies of any device to the PCI bus are usually eight cycles, but the total latency can be set from 16-256 cycles. This shows that the same word is used to describe two entirely different parameters, the first being the time until any transactions can start, the second referring to the time that is available for transactions (minus the access latencies). As an example, a PCI latency of 32 will carry a penalty (access latency) of 8 cycles which leaves 24 cycles for actual data transfers. Therefore, decreasing this latency will not increase performance, on the contrary.
The exact same is true for tRAS short for the RAS Pulse width. Historically, tRAS was defined as the time needed to establish the necessary potential between a bitline pair within the memory array until it was safe to write back the data to the memory cells of origin after a (destructive) read. Pay attention to the word read here.
Memory, in many ways is like a book, you can only read after opening a book to a certain page and paragraph within that particular page. The RAS Pulse Width is the time until a page can be closed again. Therefore, just by definition, the minimum tRAS must be the RAS-to-CAS delay plus the read latency (CAS delay). That is fine for FPM and EDO memory with their single word data transfers. With SDRAM, memory controllers started to output a chain of four consecutive quadwords on every access. With DDR, that number has increased to eight quadwords that effectively are two consecutive bursts of four.
Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers).
Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory controller to close the page “in your face!” over and again and that will cause a performance hit because of a truncated transfer that needs to be repeated. Along with those hassles comes the self-explanatory risk for data corruption. That one is not a real problem as long as the system is kept running but in case it is shut down and the memory content is written back to the hard disk drive, the consequences can be catastrophic. For the drive, that is
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