-=DVS=-
08-12-02, 03:19 PM
HOLY CRAP AMD IN TROUBLE READ THIS
We are all hearing rumours of NV30 delays as the try and get the tape out finalised on 0.13 micron technology. SO here is an interesting article from anandtech looking at how IBM is already showing working samples of 6MB caches at over 2GHz on 0.09 micron technology.
Have a gander at the near future, Imagine NV35 and NV40 's potential once they move to 0.09 micron fabrication, and a CPU with 100M transistors by 2007, just how many transistors a GPU will have then:
http://www.anandtech.com/news/shownews.html?i=15766&t=an
Date: March 12th, 2002 2:59 AM
Author Anand Lal Shimpi
Just two weeks ago Intel officially introduced the successor to the Pentium 4 under the codename Prescott. To be released in the second half of 2003, Prescott will be Intel's first 0.09-micron (90nm) CPU that will feature the following:
- Hyper-Threading technology
- Micro-architectural enhancements
- Additional L2 cache
- 800MHz FSB (200MHz Quad-Pumped)
- 90nm manufacturing process
- Close to 100,000,000 transistors
Intel has repeatedly shown graphs of where they expect CPU transistor counts to be over the next decade. Prescott's 2003 release places its transistor count at very close to 100 million transistors, meaning that it's going to be one very complicated and cache-filled desktop chip.
Today Intel announced that they have produced a fully functional 52Mbit SRAM (6.5MB) based off of the 90nm process that will be used for the Prescott core. While Prescott won't feature nearly as large of a L2 cache, the SRAM cells used in this demonstration silicon are identical to those that will be used with Prescott.
The production of this 52Mbit SRAM is important for a few reasons; first it shows that Intel's 90nm production is coming along quite nicely. When designing an SRAM circuit the basic interconnects and wiring are the same that are used in conventional CPUs; the main difference being that SRAM circuits are considerably less complex than the adders, bus interface units, multiplexers, etc… of a fully functional CPU. Towards the end of 2002 Intel will begin to demonstrate more complex logic (potentially in the form of ALUs) using this 90nm process.
Currently, the 52Mbit SRAM produced on Intel's 90nm process is running at higher clock speeds than anything currently coming out of Intel's fabs. Mind you that the highest clocked silicon being mass-produced out of Intel's fabs is between 2.2 and 2.4GHz. For a manufacturing process that is still over a year from making its public debut, being able to produce circuits operating at more than 2.2GHz is impressive.
A 300mm wafer can hold 120 billion 90nm transistors
Intel's 90nm process will be exclusively used on 300mm wafers which will help Intel manage the costs of their comparatively large die CPUs. This 52Mbit cache features a total of 330 million transistors and a 109.08 mm^2 die size; to put things in perspective, that's a bigger chip than the Coppermine Pentium III and almost the size of the Athlon XP yet it's all cache.
The 109mm^2 die features a highly repetitive structure as you can see from the above picture. This is because laying out SRAM is highly repetitive and thus makes using SRAM as the first trial of a new manufacturing process common practice in the industry.
To push the limits even further, Madison will feature a 6MB L3 cache built on the 0.13-micron process, with a 90nm Montecito core Intel may be tempted to go beyond a 10MB on-die L3 cache. These 90nm SRAM transistors are exactly 1/2 the size of the 130nm (0.13-micron) SRAM transistors used in the 0.13-micron Northwood processors; this means that without increasing the die size of the CPU Intel would be able to outfit their desktop CPUs with a 1MB L2 cache on their 90nm process.
Another advance that Intel is demonstrating with their 90nm 52Mbit SRAM is the industry's smallest 6-transistor SRAM cell size. Any cache is made up of a number of SRAM cells, each cell consisting of generally anywhere between 4 and 6 transistors. When put together, these cells form the multi-kilobyte or multi-megabyte caches that we see on a daily basis (e.g. the Pentium 4's 512KB L2 cache or the Athlon XP's 256KB L2 cache). The smaller these cells can be made, the more cache can be used within a fixed area of silicon. With their 90nm technology Intel is able to produce a 6T SRAM cell in the space of 1 square micron. Let's compare this with what TSMC just announced last week about their 90nm manufacturing process:
SRAM Size Demonstrated Cell Size
Intel's 90nm process (P1262) 52Mbit (6.5MB) 1 um^2
TSMC's 90nm process 1Mbit (128KB) & 4Mbit (512KB) 1.36 um^2
As you can see, with a smaller cell size Intel's 90nm process can achieve greater SRAM densities. By the end of 2002 TSMC hopes to get their 90nm SRAM cell size down to 1.27 um^2, still shy of the 1 um^2 achievement.
When combined with 300mm wafers, Intel's 90nm manufacturing process should be very friendly towards future-generation, larger cache CPUs. Intel will definitely be tempted to bring more features as well as larger caches to all of their CPUs once this 90nm/300mm wafer transition begins.
Meanwhile AMD will continue to manufacture on 200mm wafers until 2005 but their 130nm processor cores have small enough footprints that this shouldn't be much of an issue.
All this from 3dgpu (http://www.3dgpu.com/yabb_se/index.php?board=2;action=display;threadid=1104)
We are all hearing rumours of NV30 delays as the try and get the tape out finalised on 0.13 micron technology. SO here is an interesting article from anandtech looking at how IBM is already showing working samples of 6MB caches at over 2GHz on 0.09 micron technology.
Have a gander at the near future, Imagine NV35 and NV40 's potential once they move to 0.09 micron fabrication, and a CPU with 100M transistors by 2007, just how many transistors a GPU will have then:
http://www.anandtech.com/news/shownews.html?i=15766&t=an
Date: March 12th, 2002 2:59 AM
Author Anand Lal Shimpi
Just two weeks ago Intel officially introduced the successor to the Pentium 4 under the codename Prescott. To be released in the second half of 2003, Prescott will be Intel's first 0.09-micron (90nm) CPU that will feature the following:
- Hyper-Threading technology
- Micro-architectural enhancements
- Additional L2 cache
- 800MHz FSB (200MHz Quad-Pumped)
- 90nm manufacturing process
- Close to 100,000,000 transistors
Intel has repeatedly shown graphs of where they expect CPU transistor counts to be over the next decade. Prescott's 2003 release places its transistor count at very close to 100 million transistors, meaning that it's going to be one very complicated and cache-filled desktop chip.
Today Intel announced that they have produced a fully functional 52Mbit SRAM (6.5MB) based off of the 90nm process that will be used for the Prescott core. While Prescott won't feature nearly as large of a L2 cache, the SRAM cells used in this demonstration silicon are identical to those that will be used with Prescott.
The production of this 52Mbit SRAM is important for a few reasons; first it shows that Intel's 90nm production is coming along quite nicely. When designing an SRAM circuit the basic interconnects and wiring are the same that are used in conventional CPUs; the main difference being that SRAM circuits are considerably less complex than the adders, bus interface units, multiplexers, etc… of a fully functional CPU. Towards the end of 2002 Intel will begin to demonstrate more complex logic (potentially in the form of ALUs) using this 90nm process.
Currently, the 52Mbit SRAM produced on Intel's 90nm process is running at higher clock speeds than anything currently coming out of Intel's fabs. Mind you that the highest clocked silicon being mass-produced out of Intel's fabs is between 2.2 and 2.4GHz. For a manufacturing process that is still over a year from making its public debut, being able to produce circuits operating at more than 2.2GHz is impressive.
A 300mm wafer can hold 120 billion 90nm transistors
Intel's 90nm process will be exclusively used on 300mm wafers which will help Intel manage the costs of their comparatively large die CPUs. This 52Mbit cache features a total of 330 million transistors and a 109.08 mm^2 die size; to put things in perspective, that's a bigger chip than the Coppermine Pentium III and almost the size of the Athlon XP yet it's all cache.
The 109mm^2 die features a highly repetitive structure as you can see from the above picture. This is because laying out SRAM is highly repetitive and thus makes using SRAM as the first trial of a new manufacturing process common practice in the industry.
To push the limits even further, Madison will feature a 6MB L3 cache built on the 0.13-micron process, with a 90nm Montecito core Intel may be tempted to go beyond a 10MB on-die L3 cache. These 90nm SRAM transistors are exactly 1/2 the size of the 130nm (0.13-micron) SRAM transistors used in the 0.13-micron Northwood processors; this means that without increasing the die size of the CPU Intel would be able to outfit their desktop CPUs with a 1MB L2 cache on their 90nm process.
Another advance that Intel is demonstrating with their 90nm 52Mbit SRAM is the industry's smallest 6-transistor SRAM cell size. Any cache is made up of a number of SRAM cells, each cell consisting of generally anywhere between 4 and 6 transistors. When put together, these cells form the multi-kilobyte or multi-megabyte caches that we see on a daily basis (e.g. the Pentium 4's 512KB L2 cache or the Athlon XP's 256KB L2 cache). The smaller these cells can be made, the more cache can be used within a fixed area of silicon. With their 90nm technology Intel is able to produce a 6T SRAM cell in the space of 1 square micron. Let's compare this with what TSMC just announced last week about their 90nm manufacturing process:
SRAM Size Demonstrated Cell Size
Intel's 90nm process (P1262) 52Mbit (6.5MB) 1 um^2
TSMC's 90nm process 1Mbit (128KB) & 4Mbit (512KB) 1.36 um^2
As you can see, with a smaller cell size Intel's 90nm process can achieve greater SRAM densities. By the end of 2002 TSMC hopes to get their 90nm SRAM cell size down to 1.27 um^2, still shy of the 1 um^2 achievement.
When combined with 300mm wafers, Intel's 90nm manufacturing process should be very friendly towards future-generation, larger cache CPUs. Intel will definitely be tempted to bring more features as well as larger caches to all of their CPUs once this 90nm/300mm wafer transition begins.
Meanwhile AMD will continue to manufacture on 200mm wafers until 2005 but their 130nm processor cores have small enough footprints that this shouldn't be much of an issue.
All this from 3dgpu (http://www.3dgpu.com/yabb_se/index.php?board=2;action=display;threadid=1104)