G80 core size is 480mm2?

[AthlonXP1800]

According to the Inquirer:

G80 is already huge, 480mm2 or so, a little bigger than the R600

http://www.theinq.com/default.aspx?article=35406

[lightman]

Bah. More bull**** from the Inq. They were denied access to the latest editor's day, and now they're spewing **** all around. Morons.

[Spyke]

So you're saying 700M transistors @ 90nm is going to be small?

[lightman]

So you're saying 700M transistors @ 90nm is going to be small?

First off, the 700M figure is still unconfirmed.

Secondly, provided it's really 700M, no, it's not going to be small, but to claim 480mm2 (that's 24mm X 20mm) is simply absurd... even using a 12" wafer, that'd mean about 20-25 dies for each wafer, thus maybe 10 usable ones (the ones on the edge usually are lower quality), thus making the chip way more expensive that what you could even think. It's not gonna happen.

But, if you want to believe the 480mm2 figure, got for it. We'll see who's right in about 8 days ;) :)

[JoKeRr]

i think the inq. measured the "die size" without taking off the IHS. :o

[fellix]

I don't think so - sqrt from 480mm² results in 21x21mm footprint area of the core, which is a tag higher than say R580 (18x19.5mm).
That said, it's sounds quite plausible.

[Dazz]

Does sound about right really when you think about it. After all with prices being far in excess of $600 it may have limited availiblity which is too be expected. The GTS will be the GTX cards that just could quite make it. Might be why they are clocked lower and have less streaming processors.

[chipguy]

Secondly, provided it's really 700M, no, it's not going to be small, but to claim 480mm2 (that's 24mm X 20mm) is simply absurd... even using a 12" wafer, that'd mean about 20-25 dies for each wafer, thus maybe 10 usable ones

My elementary school math gives a maximum of 150 dies per wafer: 3.14*((12/6)*25.4)^2/480. In reality, it will be more around 120 or so. Not too bad if you put enough redunancy circuits in your chip.

(the ones on the edge usually are lower quality),

My professor of semiconductor manufacturing forgot to mention this. Probably a state-of-the-art new development?

But, if you want to believe the 480mm2 figure, got for it. We'll see who's right in about 8 days ;) :)

Yes, we'll see.

BTW: if a G71 has a die size of 196mm2 for 278m transistors, 700m transistors in the same technology would give you 493mm2. But in practice it'd be less since the high density areas is quite a bit less and not everything scale linearly.

I find 480mm2 not hard to believe at all...

[lightman]

My elementary school math gives a maximum of 150 dies per wafer: 3.14*((12/6)*25.4)^2/480. In reality, it will be more around 120 or so. Not too bad if you put enough redunancy circuits in your chip.

Err. My fault. Dunno how I came up with that figure ...

My professor of semiconductor manufacturing forgot to mention this. Probably a state-of-the-art new development?

Well, my 3+ months at ST checking chip wafers tell me that you usually throw away quite a number of the chips on the border... ;)

(btw, should anyone offer you to work at the quality control in a semiconductor company, tell him to fsck himself. Horrible work, your eyes will be ****ed up and every time you need to pee, you have to go through 20mins of trouble taking off your work suit, pass the cleaning phase, and then back in the suit and through the cleaning. Bah. I'll never do it again. :D)

[chipguy]

Well, my 3+ months at ST checking chip wafers tell me that you usually throw away quite a number of the chips on the border... ;)

Touche. :)
But can you explain why? Again, none of mathematical yield models take this into account. There's not really a good reason why defects should decide to congregate at the borders of a wafer, are there?

Horrible work, your eyes will be ****ed up and every time you need to pee, you have to go through 20mins of trouble taking off your work suit, pass the cleaning phase, and then back in the suit and through the cleaning. Bah. I'll never do it again. :D)

I only went into the fab a couple of times: thought it was funny to walk around in the bunny suit. And the place is *very* well airconditioned!

But wouldn't want to work there...

[lightman]

Touche. :)
But can you explain why? Again, none of mathematical yield models take this into account. There's not really a good reason why defects should decide to congregate at the borders of a wafer, are there?

I sincerely don't know. :D

But, one thing that surely plays a role is the inherent problems in obtaining a perfect defect-free silicon crystal with current processes. Fundamentally, during the growth of the silicon crystal it's quite frequent to have oxidation induced stacking faults, and under some circumstances, you have ring-shaped OSFs, that (I'm not really sure exactly why) tend to develop more on the periphery of the silicon wafer, thus giving you a higher probability of defects in the chips in that area, and thus lower yields...

That's as much as I recall from my job at ST ;) Right now I'm back to my research on physics and biophysics, and to tell the truth, silicon growth is the last of my thoughts :D (pirate)

[fellix]

Start to count, folks! :D

[AthlonXP1800]

Start to count, folks! :D

Is this for real or some photoshop?

I think I counted 120 chips. :D

[Razor1]

Touche. :)
But can you explain why? Again, none of mathematical yield models take this into account. There's not really a good reason why defects should decide to congregate at the borders of a wafer, are there?



I only went into the fab a couple of times: thought it was funny to walk around in the bunny suit. And the place is *very* well airconditioned!

But wouldn't want to work there...

The errors in the outside chips could be due to errors in the actual silicon which tend to be more on the outside of the wafer.

Edit:

oh didn't see lightman's response which is very correct :)

[fellix]

I've made it using CorelDRAW X3, but actually I tend to use ACAD because it's more intuitive to set and align the dimensions, for this kind of drawings. But never mind.
My approach was like this -- from the known die area [480mm*²] I take the sqrt to figure out the dimensions of the rectangle [in the case of sqrt function, it will be a square, obviously]. Of course, we can't be sure that the actual die is an exact square rectangle, but that or ether way the area is the same, right!
Then -- the easiest part -- I draw a circle with 300mm in diameter, representing the wafer itself, and finally multiplying the [square] rectangles over it then removing all the dies, crossing the edge of the wafer, and here we see the picture.

Of course, there should be an analytical path to find how much integral pieces [at any size] could be fitted in any given wafer area, but I didn't bother to figure it out (yet).

p.s.: given the conjectural price of producing a single 300mm wafer to be $12'000, that would imply that a single piece of G80 sliced out of the platter will be $100~$120 each, and that's without the post-processing stages of packaging and testing (although, that's a small fraction of the whole production cost). Then there it comes to the "randeman" -- how many of these cores would become a full healthy 128 SP parts, how many can be well "enough" for the 96 SP parts, and the rest wouldn't work at all (worst cases, but maybe in some time, they will pile up enough SKU's that would become middle-end parts with even more disabled Stream Processors).
So you see, that [initial] pricing of these new babies is something to scream about -- a matter of trade offs.