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-   -   the truth about MTRR's and PAT? (http://www.nvnews.net/vbulletin/showthread.php?t=133270)

surfer300ZX 05-21-09 12:53 PM

the truth about MTRR's and PAT?
I have a basic understanding of what MTRR's are. In my experience due to a buggy BIOS, linux has a lot of trouble setting these up correctly on boot. My goal is to set them all up by hand, but even after extensive research, I'm still unclear about a few things.

1. How does the PAT relate to MTRR's? Do they work together or does having PAT enabled eliminate the need for MTRR entries?

2. I understand the video memory should be marked as type "write-combining". Are the write-back and uncachable entries necessary? Is it OK to have memory space that's not assigned to any MTRR?

3. This is an example of one I set up by hand on my LanParty NF4 with 8800 GTS 512MB card. The card has 512MB memory but (for whatever reason) linux only lets me use 256MB @ d0000000. (according to Xorg.log and lspci)

reg00: base=0x000000000 ( 0MB), size= 2048MB, count=1: write-back <--- (kernel created)
reg01: base=0x07ff00000 ( 2047MB), size= 1MB, count=1: uncachable <--- is this necessary? (kernel created it)
reg02: base=0x080000000 ( 2048MB), size= 1024MB, count=1: uncachable <--- is this necessary? (i created as placeholder)
reg03: base=0x0c0000000 ( 3072MB), size= 256MB, count=1: uncachable <--- is this necessary? (i created as placeholder)
reg04: base=0x0d0000000 ( 3328MB), size= 256MB, count=1: write-combining <--- my video memory (this one is correct)

4. If I do a "lspci -v" I see that my card is actually reserving 3 sections in memory... one 256MB, one 16MB, one 32MB. What are the 32MB and 16MB entries for?

5. How do you manipulate the PAT in linux? (ex: the MTRR's have a /proc/mtrr interface)

Please help me understand all this.


zander 05-21-09 01:06 PM

Re: the truth about MTRR's and PAT?
1. the PAT complements the MTRRs, it does not replace them completely; for more information, please see e.g. the IA-32 Intel® Architecture Software Developer’s Manual Volume 3: System Programming Guide.

2. write-back entries are required to mark address ranges write-back cacheable (e.g. RAM); uncacheable entries are needed to create uncacheable ranges in larger write-back ranges, e.g. for I/O apertures. Address ranges that do not have an MTRR associated with them default to uncacheable.

3. if you are using the NVIDIA Linux graphics driver, you do not need to manually configure MTRRs, the driver will take the steps necessary to ensure mappings of both system memory and GPU BARs have the correct memory types.

4. BAR0 is the register aperture, BAR1 and BAR2 are driver configurable apertures (BAR1 maps to video memory by default).

5. due to the way the PAT works, there's no user-visible configuration interface.

surfer300ZX 05-21-09 01:39 PM

Re: the truth about MTRR's and PAT?
OK. That helps a lot. Just to clarify, the nvidia driver sets everything up properly, even if nothing is listed in /proc/mtrr, correct?

zander 05-21-09 02:21 PM

Re: the truth about MTRR's and PAT?
@surfer300ZX: unless you see an error message from the NVIDIA kernel module indicating that PAT support is unavailable/disabled (which shouldn't normally happen), the driver should do the right thing(tm) without modifying the MTRR configuration. If it can't use the PAT, it falls back to MTRRs to the extent possible, in which case /proc/mtrr would reflect any changes made by the driver.

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