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Old 03-04-10, 01:26 PM   #5
shadow001
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Join Date: Jul 2003
Posts: 1,526
Default Re: First benchmarks of GTX 470

Quote:
Originally Posted by Redeemed View Post
I'm not GPU-architect-engineering-guru but...

It seems I recall the 7800GTX was under whelming, and the refresh, on the same process was leaps and bounds better (7900GTX). If nVidia managed it with the 7900- why couldn't they here? Who knows what is going on under the hood- maybe a lot of power leakage? I mean, there's a reason it's inefficient. It's possible, I'd imagine, they could fix this with a refresh? Maybe?

Well for one,you're mentioning a GPU with about 350 million transistors in it,and those GPU's used a lot less power to begin with,so it was easier on the cooling front as well,while fermi is 3 billion transistor processor afterall,is much larger and looks to use a lot more power.


The only chip that was close to Fermi's size in Nvidia's history was the original G80 GPU,when built at the 65 nm process,at about 576mm^ and it also used a 6 + 8 pin PCI-e power connector arrangement,using about 225 watts,but even then,the G80 was about 780 million transistors,give or take.


Fermi is a 3 billion transistor monster,and while the 40nm process also allows to reduce power consumption to a nice degree and make the actual die size small enough(relatively speaking here),to allow it to be built in volume,there are limits to it in the end,and there is an 850 million transistor difference between it and ATI's Cypress chip used on that very same TSMC process.


Regardless of how Fermi ends upin terms of gaming performance,that's still 850 million extra transistors that are being powered up and generating heat as they operate,so power consumption is higher,yeilds are lower(even if 100% of the chips were good) and so are the problems with keeping it running cool,or trying to make a dual GPU version of it.


Transitioning from 40nm down to 28nm,would cut the die size of fermi to about 1/2 of what it is at 40nm,so we'd see it shrink to about 250mm^(assuming Fermi is slightly over 500mm^ at 40nm),wich is a large drop and allows for options that simply aren't feasable at 40nm,even if no other changes are made to the architecture itself,which there will be for sure.
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