Originally Posted by josiahsuarez
don't be fooled by that graph; "DP GFLOPS per Watt"
the graph is about efficiency, not absolute performance.
True, but going from a 40 nm fab process, which is what fermi still uses as we all know, to a 28nm process is a 60% reduction(transistor lenght and height), so if the ratio between logic circuits and cache is similar between kepler and fermi(cache can be packed closer together), it allows a 60% increase to the overall transistor budget while maintaining the same die sizes and production costs(if yeilds are good of course), and fermi is packing 3.2 billion transistors.
So 3.2 billion transistors at 40nm + 60% and assuming the same die size for both fermi and kepler = 5.1 billion transistors at 28nm for kepler....Obviously i haven't considered power consumption or cooling issues here, wich are variables we'd only know if TSMC was willing to divulge said information about their 28nm process( unlikely without having a licence with TSMC...
Fermi is rated at 240 watts TDP and that's only 60 watts short of the maximum limit for PCI-e compliance(300 watts), so can Kepler double performance over fermi with the 60% increase in transistor budget, cost the same to produce as fermi since it's the same die size, and remain under that 300 watt limit for PCI-e compliance?.... Wait 6 months to find out(if not more)...