Originally posted by SnapIT
Well, hopefully intel will realize their mistake and implement it, without it, the cpu in itself needs a bugfix, can you imagine the overhead for such a bugfix in sw in a separately loaded part of nvram? every single instruction would have to pass through... or just give it up and realize that you have a wide open system no matter what you do...
Actually, a sw fix is pretty easy with only a small performance hit. When a page fault occurs, set the MMU tables and do an access to force the TLBs to load the entry, then go back and use the test registers to invalidate the instruction TLB for that page. This leaves the data TLB with a valid translation, but any instruction accesses will cause another page fault. In the second page fault, simulate the no-execute. This works on x86 CPUs allowing access to the TLB through the test registers AND uses separate TLBs for data and code access. This means you can simulate NX with a little extra code in the page fault handler of Pentium and newer chips, but not on the 486 or older. The 486 allows the access of the TLB via the test registers, but only had one TLB to handle both data and code.