Join Date: Feb 2008
Location: Dallas, Texas
CMOS scaling... beyond 10nm!
this is a bit of good news, I think
CMOS technology scaling will go on for the foreseeable future but, as we enter the 10nm node, process complexity reduction and variability control will become crucial and drive technology decisions, said An Steegen, senior vice president process technology at Imec, at the annual IMEC Technology Forum last week at the Square meeting center in Brussels, Belgium.
Tomorrow’s smart systems will require more computing power and storage capacity, exceeding what today’s processors and memories can deliver. This drives the need for technology scaling.
In her keynote, Steegen explained how Imec is helping to enable chip scaling beyond 10 nm. Moore’s Law through 19 nm can be lithography-enabled but, after that, it is necessary to look at materials and new design architectures.
Steegen’s message was that CMOS scaling is still possible. It’s just harder. Driving to sub-15nm dimensions requires EUV lithography and advanced patterning. It also implies a migration towards 3D device architectures such as FinFET and calls for material innovation with high-mobility channel materials.
Moore’s law continues but, Steegen specified, it increases complexity, cost and variability. New technology and design solutions together with co-optimization are required.
“The good news is that CMOS still scales, from planar Si device architectures (20 nm) to FinFET device architectures (14 nm) to better control short channel effects. But when you scale, when you introduce new materials, variability increases,” she stated.
In a post-conference discussion with EE Times, Steegen provided more details on the variability issue as we move beyond 10 nm.
“Moving to fully-depleted channel devices like FinFET, allowing us to minimize doping in the channel, we have alleviated some of the variability issues associated with random dopants,” Steegen explained. “This is reflected in the reduced device mismatch. However, with non-planar devices, new variability emerges. With sidewall conduction and increase surface-to-volume ratio, trap and defect induced variation (eg. Low-Freq Noise, BTI reliability, etc.) become more important.
She continued: “Some of these new factors carry into 10nm technology. Beyond this, we expect new variability influences due to new material in the channel and advanced gate-stack modules introduced to boost device performance. New random defects may arise from the challenging integration (eg. Selective epitaxial growth of the heterostructure). Moreover, this material alters the interaction between the channel carriers and the traps/defects giving rise to changes in reliability, and noise.”
When asked what needs to be done to ease the variability issue, Steegen explained that Imec is looking into engineering the material to improve on quality.
There is also fundamental study on how to engineer the energy bands of the channel material to optimize reliability and performance. For instance, she noted, “we have looked into the engineering of implant-free quantum well SiGe channel devices to improved NBTI reliability. Work is ongoing to study the approach for FinFET devices for beyond 14nm applications.”
Steegen explained that, as part of the program, Imec is working to identify paradigm shifts in design. The research institute explores potential solutions, some of which require support by EDA tools. For that purpose, Imec collaborates with EDA vendors in such diverse domains as 3D Design-For-Test, TCAD, impact of litho options on P&R, OPC, 3D system design exploration, etc.
Her last words at the conference were encouraging. “Variability and cost must be considered as from the beginning. We have been reinventing ourselves many many times in the semiconductor industry. We will do it again and again,” she concluded.